Electrostatic Discharge (ESD) induced failure is a major concern for the Metal-Oxide-Semiconductor (MOS) transistor-based integrated circuits (ICs) in main-stream technologies. This reliability issue is further worsened in advanced technology including submicron Complementary-Metal-Oxide-Semiconductor (CMOS) with very low operation voltage (such as an operating voltage <5V) and Bipolar-CMOS-DMOS (BCD) for high voltage applications. There has been a growing demand for the availability of robust ESD protection solutions for advanced and main-stream technologies that are capable of operating in a very narrow ESD design window. A Silicon Controlled Rectifier (SCR) is a common device used for ESD protection.
A typical on-chip ESD protection scheme for an I/O port (generally accessible at a bond pad on the IC die) involves including an SCR device referred to as an ESD clamp hooked in parallel to the internal circuitry to be protected between the input/output (I/O) pad which interfaces to both the outside world and ground (GND). When an ESD event (e.g., a high power pulse) occurs at the I/O port, the ESD clamp turns on and once on provides a parallel low resistance conduction path that shunts the ESD-induced current (and thus the power) to GND, and thus away from the internal circuitry being protected.
FIG. 1A shows a cross-section view of a conventional SCR 100 and FIG. 1B the equivalent circuit of the conventional SCR 100. SCR 100 includes a parasitic PNP bipolar transistor 110 including an nwell 111 as its nbase and a parasitic NPN bipolar transistor 120 including a pwell 121 as its pbase, where the (C) collector of each transistor is coupled to the base (B) of the other transistor.
SCR 100 is a 4 terminal device having 4 surface terminals formed on a substrate 102 shown having a semiconductor p-type surface (p-sub) 105. Typical doping concentrations in p-sub 105 are 1×1015 cm−3, in nwell 111 from 1×1017 to 1×1018 cm−3, and in pwell 121 from 1×1017 to 1×1018 cm−3. Typical junction depths for nwell 111 and pwell 121 are 1 μm to 1.5 μm.
The terminals of SCR 100 are identified as “anode gate” (AG) 112/N+ region formed at the surface of the nwell 111, “anode”/P+ region 113 formed at the surface of the nwell 111 lateral to the AG 112, “cathode gate” (CG)/P+ region 122 formed at the surface of the pwell 121, and “cathode”/N+ 123 formed at the surface of the pwell 121 lateral to CG 122. In SCR 100, the AG 112 and anode 113 in the nwell 111 are both seen to be connected to I/O PAD (PAD, the PAD to be ESD protected), while the cathode 123 and CG 122 in the pwell 121 are both seen connected to GROUND (GND). Thus, in conventional SCR 100, the AG 112 and anode 113 are tied together and connected to the I/O PAD, while CG 122 and the cathode 123 are tied together and connected to GND.
Conventional SCR 100 and its variants use a triggering circuit outside the SCR region to turn on the SCR 100 which takes up area on the chip. Known SCRs generally have a relatively high trigger voltage and leakage current, and process snapback behavior, which make it hard to work in smaller ESD design windows. Moreover, conventional SCR 100 and its variants have a relatively slow turn-on speed which can prove fatal to some relatively EDS-sensitive internal circuitry in the case of a fast-rising ESD stress.